With increases in processor capability and performance, the demand for more functionality from electronic devices increases. The increased functionality in turn increases processor bandwidth demand, which is related to higher overall data throughput. Thus, the inability to move data into and out of the processor with higher bandwidths can impede the continuation of processor performance improvements. Modern computing systems include layers of memory, from the fastest, smallest on die memory storage (e.g., cache), to main memory, to larger and slower nonvolatile storage. Higher processor throughput typically requires moving more data into main memory from nonvolatile storage, and then moving that data between main memory and cache layers on the processor.
Traditional connection of the main memory to the processor is via native memory channels. Native memory channels rely on a direct connection from the memory devices to a controller circuit or memory manager/driver on the host processor. Traditional memory connection occurs through multidrop channels, where the signal lines of a memory channel extend to multiple memory devices, from devices mounted physically closest to the processor to the devices mounted physically farthest from the processor. The devices connect in turn and drive and/or terminate the same signal lines.
Multidrop channels limit the number of memory devices that can be connected to a processor, which limits the memory capacity of a system. When more memory devices and memory modules are connected with multidrop connections, the loading on the memory channel can degrade the communication over the bus. Thus, there is a tradeoff between increasing the speed and increasing the capacity in a memory subsystem. The tradeoff represents a potential limitation in the ability of memory bandwidth to continue to scale to processor performance. Current systems are already hitting the data rate limit for a native multidrop memory channel with two memory modules installed. While increasing the number of channels can help with the data rate problem, it is not scalable with processor performance increases. Increasing channel bandwidth may also be impractical because of increasing the number of signal lines, as well as increasing device and connector size to accommodate the additional signal lines.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.